A research team from Fudan University has discovered a novel basic architecture for chips that is expected to achieve higher area efficiency through halving the space of logic gate, or the elementary building block of a digital circuit.
The study, led by professors Zhang Wei and Zhou Peng at Fudan University’s School of Microelectronics, will soon be published on Nature Nanotechnology, a top-notch academic journal covering nanoscience and nanotechnology.
Such a prototyped transistor is based on a two-dimensional material that can realize photo-swtiching logic computing in a single cell, thanks to its two-surface channels, said Zhang.
This is likely to extend Moore’s Law, an observation that the number of transistors in a dense integrated circuit doubles about every 18 months. The theory has in recent years been challenged by industrial players as they face mounting difficulties in further scaling down chips in size.
Another primary breakthrough is the development of an architecture that can be flexibly expanded to achieve both computing and data storage at the same time. And the consequent shrunken size of chips will greatly improve computing performance and further lower costs.
“These devices show the potential of becoming promising candidates for the construction of new chips that can perform computing and storage with unique functions and with high area-efficiency,” Zhou said.
“The work opens up new horizons for seeking promising solutions to future electronic device and novel circuit architecture…The exceptional application concept for next-generation integrated circuits of two-dimensional semiconductors will open a new gate to the computing and memory,” according to a statement from the journal’s review committee.